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bulletA simple lumped electrical model for an RF MEMS switch considering lossy substrate effects

Giuseppe Cusmai, Marco Mazzini, Paolo Rossi, Chantal Combi, Benedetto Vigna and Francesco Svelto

This work focuses on electrostatically actuated micro-electro-mechanical systems (MEMS) capacitive switches, intended for adaptive output stage of power amplifiers. These devices are particularly attractive because theoretically they are capable of very high quality factor values due to the air gap between plates and the low resistivity of lines and bridge. On the other hand, substrate parasitic effects, overlooked up to date, can seriously impair device performance. In this paper, we introduce a lumped element equivalent circuit taking into account substrate effects. Model validation is based on measurements carried out in the 50 MHz–40 GHz range.

ELSEVIER SENSORS AND ACTUATORS A: PHISICAL, VOL 123, SEPTEMBER 2005

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bulletExperimental Study and Modeling of the White Noise Sources in Submicron P- and N- MOSFETs

V. Re, I. Bietti, R. Castello, M. Manghisoni, V. Speziali, and F. Svelto

This paper presents the results of the experimental characterization of the channel thermal noise in MOSFETs belonging to a submicron gate process, with minimum gate length L = 0.35 µm. The data are compared with a noise model taking into account short-channel effects such as velocity saturation and hot carriers. The contribution of gate and substrate parasitic resistors is also evaluated and included in the model. The analysis is carried out for devices with various gate geometries, investigating the behavior of the noise-related parameters in the range of small gate-to-source overdrive voltages, which is of major concern for low-power circuits.

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 48, NO. 4, AUGUST 2001

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bulletA Three Terminal Varactor for RF IC's in Standard CMOS Technology

F. Svelto, S. Manzini, and R. Castello

A three terminal metal-oxide-silicon varactor operated between accumulation and deep depletion is proposed for rf IC’s. Prototypes, realized in a 0.35 µm standard CMOS technology, show a 3.1:1 capacitance tuning. The corresponding minimum Q is 23 at 1800 MHz. The proposed varactor lends itself as tuning element of VCO’s in highly integrated CMOS transceivers.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 4, APRIL 2000

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bulletAn Innovative Modelization of Loss Mechanism in Silicon Integrated Inductors

Paolo Arcioni, Rinaldo Castello, Luca Perregrini, Enrico Sacchi, and Francesco Svelto

In this paper, we present an improved lumped-element equivalent circuit of silicon integrated inductors, which accurately takes into account parasitic effects and separately models the effect of metal and substrate losses. We describe an efficient procedure to deduce all the elements of the equivalent circuit from wideband, two-port measurements of the S-parameters of the inductor. The separate characterization of metal and substrate losses allows us to evaluate separately their contribution to the inductor’s Q-factor. We also report the results of the characterization of some CMOS and BiCMOS integrated inductors designed to be included in radio frequency integrated circuits operating at 1.8 GHz.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 12, DECEMBER 1999

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bulletA Metal – Oxide – Semiconductor Varactor

F. Svelto, P. Erratico, S. Manzini, and R. Castello

CMOS technology scaling opens up the possibility of designing variable capacitors based on a metal oxide semiconductor structure with improved tuning range and quality factor. This is due to an increase in the oxide capacitance and a reduction in the parasitic resistance. A prototype metal–oxide–semiconductor (MOS) variable capacitor of 3.1 pF nominal value has been realized in a 0.35-µm standard CMOS process. A factor two ca-pacitance change has been achieved for a 2-V variation of the controlling voltage. The varactor Q ranges from 17 to 35, at 1.8 GHz.

IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 4, APRIL 1999

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bulletMeasurement and Modeling of Si Integrated Inductors

P. Arcioni, R. Castello, G. De Astis, E. Sacchi, and F. Svelto

This work describes a method to derive from measurements an accurate lumped element model of spiral integrated inductors on silicon substrate. The analysis method is based on a wideband two - port measurement of the s - parameters of the device under test and enables an accurate evaluation of the parasitic effects that limit the performances of these integrated devices.

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 47, NO. 5, OCTOBER 1998

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bulletA ±30% Varactor Compatible with future Scaled Technologies

R. Castello, P. Erratico, S. Manzini, and F. Svelto

A ±30% capacitance modulation of a new variable capacitance has been achieved for a 2 V variation in the controlling bias voltage. The realized varactor is based on a polysilicon - oxide - nwell structure, implemented in a 0.35 µm standard CMOS process. The Quality factor of a 3.1 pF sample ranges from 17 to 33, at 1800 MHz.

Symposium on VLSI Circuits Digestof Technical Papers, 1998

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