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The group has been active in this field since 1995. This activity is aimed at the realization of fully integrated CMOS transceivers for wireless applications. Several programs have been carried on both in the framework of European (e.g. ESPRIT and MEDEA) and Italian projects (PRIN, Madess II). Contributions have been given in the analysis and optimization of passive components (inductors and varactors) and basic building blocks (LNA, mixers, VCO). More recently fully integrated front-end solutions for global positioning systems and fully integrated RF sections for 3rd generation cellular phone, namely UMTS, have been proposed. Future research activity will focus receivers for multi-standard applications and transmitters. Collaborations are presently on going with ST Microelectronics, Mindspeed Technologies, and Agere Systems. Contact People: Francesco Svelto, Danilo Manstretta
This
activity has been developed in the last two years in cooperation with Conexant
Systems / Mindspeed Technologies. We first focused on the design of the 10 Gb/s
receiver front end for the standard SONET OC-192; the designed blocks are a 0.18
μm CMOS Transimpedance plus Limiting Amplifier. The present research
activity is based on the analysis and design of a Clock and Data Recovery with
High Jitter Tolerance for the same applications, using a dual loop (DLL – PLL)
architecture. A second
activity concerning this area has been the design of an adaptive analog
equalizer for data transmission at 3.2 Gb/s in 0.18
μm CMOS. This device compensates the frequency dependent losses
typical of copper media (skin effect, dielectric losses), thus eliminating the
deterministic jitter, that makes otherwise impossible correct data recovery,
while transmitting at high bit rates on long coaxial cables or board traces. Contact People: Rinaldo Castello,
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