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Giuseppe Cusmai, Massimo Brandolini, Paolo Rossi and Francesco Svelto Abstract—This paper addresses the problem of 5–6GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18um CMOS technology, comprises a single-ended voltage– voltage feedback low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5–6GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1dB gain desensitization with a 6.5dBm interferer power at 5.5 GHz. Other measured performances are 5.2dB and 7.7dB minimum and maximum noise figure (NF), 3.5dBm minimum IIP3 and +34.5dBm minimum in-band IIP2 and +21dBm out-of-band IIP2. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 Download the paper.
Massimo Brandolini, Paolo Rossi, Danilo Manstretta, and Francesco Svelto Abstract—In the recent past, there has been an evolution in wireless communications toward multifunctions and multistandard mobile terminals. Reducing the number of external components to a minimum is key when the same mobile terminal has to process several different standards. Highly integrated solutions in low-cost silicon technologies are thus required. Zero-IF and low-IF receiver architectures are most suitable for a high level of integration. This paper presents a review of global system for mobile communications, universal mobile telecommuniation system, Bluetooth, and wireless local area network (IEEE802.11a, b, g and HiperLAN2) standards, likely to all be present in the “universal” terminal of the future, enabling global roaming and wireless connectivity. The various standards are analyzed in order to find the optimal architecture and the building-block specifications for the receive section, with particular care to the RF front-end. State-of-the- art solutions are discussed, with emphasis on direct conversion CMOS implementations. A multistandard architecture for a fully-integrated CMOS receiver is proposed. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53 NO. 3, MARCH 2005 Download the paper.
A. Bevilacqua and Francesco Svelto Nonlinear spectral analysis is exploited in this brief to investigate the second-order intermodulation distortion in direct conversion receivers (DCRs) for wideband code division multiple access systems. The emphasis is on the accurate modeling of the interferer, and on the derivation of the second-order intermodulation distortion spectra. Depending on the number of code multiplexed channels, the second-order intermodulation distortion power produced in the receiver can be significantly different. It varies by 6.5 dB between two boundary cases: multichannel versus single-channel signal. The developed analysis is verified by means of experiments carried out on a 0.18- m CMOS DCR realized for the universal mobile telecommunications system standard. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - 2, VOL. 52 NO. 3, MARCH 2005
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Paolo Rossi, Antonio Liscidini, Massimo Brandolini and Francesco Svelto Employing feedback circuits in RF front-ends can be a key aspect for easy reconfiguration of multistandard receivers. A narrow-band filter can shape the frequency transfer function and, by reflection due to the feedback network, the input impedance. Switching one single filter component thus allows selecting a different standard. We introduce a voltage–voltage feedback low noise amplifier that, besides being easily reconfigurable, shows roughly the same noise and better linearity, for same power consumption, as the conventional inductively degenerated topology. A direct conversion front-end, including the LNA and and mixers, tailored to WLAN applications in the 5–6 GHz range, has been realized in a 0.25- m SiGe BiCMOS process. Prototypes show the following performances: 2.5 dB NF, 31.5 dB gain, 9.5 dBm IIP3, and +23 dBm minimum IIP2 while consuming 16 mA from a 2.5 V supply. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40 NO. 3, MARCH 2005
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Andrea Mazzanti, Paola Uggetti, and Francesco Svelto Injection-locked LC dividers for low-power quadrature generation are discussed in this paper. Modeling the circuits as regenerative frequency dividers leads to very simple analytical expressions for the locking band, phase deviation from quadrature and phase noise. Maximizing the ratio between the injected and the biasing current is beneficial to all the above parameters whereas reducing the tank quality factor improves locking band and quadrature accuracy, though at the expense of current consumption, for given output amplitude. To validate the theory, experiments have been carried on a 0.18- m CMOS direct conversion IC, embedding an injection-locked quadrature generator, realized for the Universal Mobile Telecommunication System. Frequency locking range as large as 24% and phase deviation from quadrature around 0.8 are measured while each divider consumes 2 mA. The phase noise of the quadrature generator is determined by the driving oscillator phase noise because the dividers contribution is easily made negligible up to hundreds of megahertz offset. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 Download the paper.
Francesco Gatta, Danilo Manstretta, Paolo Rossi, and Francesco Svelto This paper presents a 0.18-μm CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous - time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, 2 dBm out-of-band IIP3, 10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and 155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 Download the paper.
Paolo Rossi, Francesco Svelto, Andrea Mazzanti and Pietro Andreani The design of radio-frequency inductively-degenerated CMOS low-noise-amplifiers does not follow the guidelines for minimum noise figure. Nonetheless, state-of-the-art implementations achieve noise figure values very close to the theoretical minimum. In this brief contribution, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device acting as transconductor. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used. IEEE Norchip Conf., November 2003 Download the paper.
M. Pisati, F. Gatta, C. Bazzani, R. Castello and F. Svelto A shunt series feedback
transimpedance amplifier (TIA), using a zero – pole cancellation,
followed by a 6 stages limiting amplifier (LA), proves to be suitable
as receiver front-end for a 8 Gb/s communications over fiber optic.
The front-end is realized with a 0.18 µm CMOS IEEE Norchip Conf., November 2003 Download the paper.
A. Mazzanti, P. Uggetti, P. Rossi and F. Svelto The trade off between phase noise and quadrature accuracy, typical of coupled voltage controlled oscillators, is broken if injection locking dividers are used for I and Q generation. Based on the general behavioral modeling of regenerative frequency dividers, this paper derives analytical expressions for locking band and phase deviation from quadrature. An injection locking quadrature generator, embedded in a 0.18µm CMOS direct conversion receiver, shows 24% frequency locking range while drawing 4mA. The phase deviation from quadrature measured on down-converted signals is 0.8°. IEEE Custom Integrated Circuits Conf., 2003 Download the paper.
D. Manstretta, M Brandolini and F. Svelto An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-µm direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003 Download the paper.
Francesco Svelto and Rinaldo Castello This paper presents a technique that optimizes-tank CMOS voltage-controlled oscillators (VCOs) by minimizing the product of phase noise and power consumption. Moreover, it shows that the minimum depends on the tank’s quality factor, the device noise coefficient, and the ratio between the maximum oscillation amplitude and supply voltage . Prototypes, realized in a 0.35-µm process, show the following performances: 122.5 dBc/Hz at 600 kHz from a 1.9-GHz carrier, with 2-V supply voltage and 1-mA current consumption. The VCO can be tuned between 1.8–2.4 GHz, when the varactor control voltage is varied between 0–3.5 V. In the proposed realization, the tank is made of a metal–oxide–silicon varactor (operated between accumulation and deep depletion) and a bond-wire inductor, realized connecting two pads to a package frame lead to be compatible with the production environment. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002 Download the paper.
F. Gatta, E. Sacchi, F. Svelto, P. Vilmercati, and R. Castello This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-µm CMOS LNA (plus output buffer) prototype achieves the following performances: 2 dB noise figure (NF), 17.5 dB power gain, -6 dBm IIP3 with 8 mA current consumption from a 2.7 V voltage supply. To the author’s knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001 Download the paper.
D. Manstretta, R. Castello, and F. Svelto The analysis of direct conversion CMOS active mixers tailored to ReFlex standard is presented. To minimize 1/f noise, the switching stage pMOS devices have large area, low biasing current. pMOS and nMOS transconductors shunt together form the input stage. A 0.35 µm prototype performs at 900 MHz as follows: 18 dB SSB NF averaged in the 100Hz – 3kHz band, 18 dB gain, - 4 dBm IIP3, 30 dBm IIP2 with 6 mA from 2.7 V supply. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 9, SEPTEMBER 2001 Download the paper.
F. Svelto, S. Deantoni, G. Montagna, and R. Castello A fully differential 0.35 µm CMOS LNA plus mixer, for GPS applications, using no external component apart from an input balun, has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by a MOS varactor. The mixer is a Gilbert cell type in which an NMOS and a PMOS differential pair, shunt together, realize the input stage. This topology allows one to save power for given mixer gain and linearity. The front-end measured performances are: 40 dB gain, 3.8 dB NF, 25.5 dBm IIP3, 1.3 GHz input frequency, 140 MHz output frequency, with 8 mA from a 2.8 V supply. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 Download the paper.
F. Svelto, S. Deantoni, and R. Castello This paper presents a low-phase noise CMOS LC-VCO, in which a complete compensation of the components spread, due to process variations, can be done. The LC tank is made of a metal–oxide–silicon varactor and the series of a bondwire and a spiral inductor. The trade-off between VCO gain variations and phase noise is introduced. The measurements performed on a prototype, powered by a 2 V supply, realized in a digital CMOS process, are presented. The oscillation frequency can be varied in the range 1.1–1.45 GHz. The measured phase noise at an offset of 600 kHz from a 1.3 GHz carrier is -119 dBc/Hz, with 6 mA current consumption. IEEE JOURNAL ON SOLID STATE CIRCUITS, VOL. 35, NO. 3, MARCH 2000 Download the paper.
F. Svelto, M. Conta, V. Della Torre, R. Castello This paper presents a 0.5 µm CMOS mixer for RF applications. The core consists of a quad differential pair, with resistive degeneration, implemented with MOS transistors in the linear region. This topology proves to be suitable for low voltage, highly linear down-converters. Compared with a CMOS Gilbert cell, it features a better linearity with a lower supply voltage. The mixer is powered at 2 V supply and drains 3.8 mA; the IIP3 and the single side band NF are given respectively by 21 dBm and 24 dB. In terms of spurious free dynamic range, the present circuit compares favorably with other reported mixers, operated at low voltage, both in bipolar and CMOS technologies. This is true even though a significant contribution to the noise figure comes from the IF stage, due to the very low supply. IEEE Transaction on Consumer Electronics, Vol. 45, No. 2, May 1999 Download the paper. |
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