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bulletAn Eighth-Order CMOS Lowpass Filter with 30-120MHz Tuning Range and Programmable Boost

G. Bollati, S. Marchese, M. Demicheli, R. Castello

A CMOS low-pass filter with programmable boost is presented. The architecture is a Gm/C type with the Gm value controlled through a resistor servo approach. The transfer function has been optimized in order to reduce the sensitivity to component parameter variations. The 1:4 tuning range is achieved by exploiting a dual-loop control over a degenerated differential pair. At the nominal output voltage swing of 200 mVpp differential, a THD better than 40 dB is guaranteed. The high-frequency boost is programmable between 6 and 14 dB. This filter, realized as a cascade of biquad and first-order cells, is implemented in a 0.25-µm 2.5-V CMOS technology. It dissipates 120 mW with fc=120 MHz and has a die area of 0.23 mm2.

IEEE Journal of Solid-State Circuits, vol. 37, no. 7, July 2001

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bulletA 200- Ms/s 10-mW switched-capacitor filter in 0.5- µm CMOS technology

A. Baschirotto, F. Severi, R. Castello

Wideband amplifiers with low but precisely known dc gain allow the achievement of accurate infinite impulse response switched-capacitor (SC) filters operating at very high sampling frequencies. The low and precise opamp gain value is taken into account while sizing the capacitors (precise opamp gain (FOG) approach), so that no idle phase is required for amplitude error compensation and double-sampling technique can be implemented. In a 0.5-µm standard CMOS technology with 3.3-V power supply, an opamp is designed which exhibits a settling time of about 3 ns (for 0.1% settling accuracy) in a closed-loop configuration with input, feedback, and load capacitors of 0.5 pF, white the slew rate is 1 V/ns. The open-loop dc gain of the amplifier is set to the value of 80 (38 dB) by a gain-control closed loop, which guarantees an accuracy of ±2%. The proposed solution is validated by experimental results from a 200-Ms/s SC filter. From a single 3.3-V supply the filter consumes 10 mW (excluding clock generation) and exhibits a -40 dB total harmonic distortion for a 2-

IEEE Journal of Solid-State Circuits, vol. 35, pp. 1215 - 1219, August 2000

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bulletA Versatile High-Speed Bipolar Charge-Sensitive Preamplifier for Calorimeter Applications

A. Baschirotto,  R. Castello, G. Pessina, P. G. Rancoita, and A. Seidman

A high-speed charge-sensitive preamplifier (CSP) to be used in silicon calorimeters has been realized. The main W output drive capability. In addition, the CSP is designed to allow adaptation of its power-versus- noise performance to different experimental conditions. The bias current of the input device can be adjusted with an external component, in order to optimize the tradeoff between power consumption and noise. The power supply can be set in the 3.3–12-V range, optimizing the power dissipation over output swing ratio. The CSP was realized in a bipolar technology whose bipolar transistors have been previously tested before and after being subjected to irradiation. The results were taken into account in the design in order to achieve CSP radiation-hard performance.

IEEE Journal of Solid-State Circuits, vol. 33, no. 4, April 1998

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bulletA 1-V 1.8-MHz CMOS Switched-Opamp SC Filter with Rail-to-Rail Output Swing

A. Baschirotto,  R. Castello

A low-voltage switched capacitor (SC) filter operated

IEEE Journal of Solid-State Circuits, vol. 32, no. 12, December 1997

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